An important factor in the design of integrated circuits relates to the power dissipation and power usage of the integrated circuits. For System-on-Chip (SoC) designs, for instance, which may integrate all or substantially all components of a system (e.g., a computer or network device) into a single integrated circuit, it can be important to efficiently use power.
For hand-held devices such as cell phones, high power usage can quickly drain batteries. On the other hand, for central office equipment such as telecommunication network devices, high power usage can cause heat dissipation problems that may prevent the equipment from working properly. Accordingly, it may be desirable to reduce power consumption by a device, such as a SoC design.
One technique for reducing power consumption is to adjust the voltage supplied to the device. The voltage supplied to the device has a parabolic relationship to power dissipated by the device. The voltage may be adjusted based on, for example, timing margins (i.e., the “extra” time between the completion of an operation and the beginning of the next operation) within a data processing path of the device. One method is to adjust the supply voltage to maintain sufficient timing margin in the device. Another method is to allow the device to produce small amount of errors due to insufficient timing margin. These errors must be first detected in many modified circuit components such as flip-flops included in the device. Then, the operation that produces errors must be re-computed at a reduced clock rate. Many possible disadvantages of this technique may exist. One possible disadvantage is that the traditional design of circuit components may need to be modified to detect the available timing margins. This can add complexity and expense to the design. Another disadvantage of this technique is the requirement to re-compute the failed operation at a lower clock rate. This requirement is not always possible in practical applications.